Method of manufacturing an electronic device

ABSTRACT

The present invention provides a method of manufacturing an electronic device provided with metal regions, that are mutually separated by air spaces. In the method a first isolating layer, a seed layer and a second isolating layer are provided before applying metal regions. The seed layer and the second isolating layer are only removed after the provision of the metal regions. The method can be advantageously applied for the manufacture of a multilevel interconnect structure and for the manufacture of micro-electromechanical elements.

The invention relates to a method of manufacturing an electronic deviceprovided with metal regions that are mutually separated by air spaces,which method comprises the steps of

fining a first isolating layer on a substrate surface;

depositing a metal seed layer so that it covers the first isolatinglayer and exposed areas of the substrate surface; and

forming at least one metal region upon the exposed seed layer.

Such a method is known form U.S. Pat. No. 6,037,248. In this methodthere is preferably provided a plurality of isolating layers and metalregions, wherein the isolating layers are photoresist layers. Eachforming of a metal region is followed by a polishing step, so as toremove the superfluous metal and the metal seed layer. Finally, theisolating layers are removed simultaneously.

It is a disadvantage of the known method that it is elaborate and uses ahigh number of metal deposition and processing steps to arrive at afinal structure.

It is therefore a first object of the invention to provide a method ofthe kind mentioned in the opening paragraph, with a reduced number ofprocessing steps to arrive at a final structure.

This object is realized in that

a second patterned isolating layer is formed on the seed layer accordingto a second pattern, a perpendicular projection of which on thesubstrate surface has an overlap with the first isolating layer;

the metal regions are formed such that they fill the patterns defined bythe first and the second isolating layers, and

the second isolating layer and the seed layer are removed after formingof the metal regions, therewith obtaining the air spaces, the seed layerbeing removed in so far as it is not covered by the metal regions.

In the method of the invention a metal region is only formed after theprovision of a first and a second isolating layer. Thereafter, or afterproviding further isolating layers and further level metal regions, theisolating layers are removed. In this removal the metal seed layer actsas etch stop layer. Hence, the number of metallisation steps and thenumber of polishing steps are cut to at least the half.

Although the number of removal steps increases, this is not dramatic,since etching is a well-controlled, clean and quick process step,especially compared to polishing. Besides, the method of the inventionhas the advantage that some of the isolating layers can be maintained ifso desired. This allows the formation of functional entities within thestructure of metal regions that are mutually separated with air spaces.

In a first embodiment the first isolating layer is removed after removalof the seed layer. In this embodiment a structure equal to the knownstructure is obtained. This embodiment is in particular advantageous ifthe pattern formed in the first isolation layer includes contact holesor vias extending to the substrate surface. The capacitive couplingbetween the vias that have to transmit signals individually, is thenreduced.

In a second embodiment the first isolating layer is not removed, butmaintained. In a preferred case a metallisation layer is present underthe first isolating layer. This allows the definition of elements suchas thin-film capacitors in the structure. It is therefore advantageousthat the first isolating layer has a high dielectric constant, forexample a relative dielectric constant of 7.0 or more. Materials thathave such a dielectric constant are for instance Si₃N₄, Ta₂O₅, BaZrTiO₃.Other materials are known to the person skilled in the art. Otherelements are for instance two-layer inductors. Therewith it isadvantageous that the first isolating layer contains a material with ahigh magnetic susceptibility, such as ferrites, composites with ferriteparticles, and the like.

In a further embodiment the method comprises before removal of thesecond isolating layer the steps of:

forming a third patterned isolating layer on the metal regions;

depositing an additional metal seed layer so that it covers the thirdpatterned isolating layer and exposed areas of the metal regions;

forming a fourth patterned isolating layer on the additional seed layeraccording to a fourth pattern;

forming second level metal regions upon the exposed seed layer, so as tofill the pattern defined by the third and the fourth isolating layers;and

removing the fourth isolating layer, the additional metal seed layer, inso far as the seed layer is not covered by the formed second level metalregions, and the third isolating layer.

In this embodiment a multilevel structure is provided. Such a multilevelstructure can be used as an interconnect structure for an integratedcircuit.

It is advantageous if in the multilevel structure amicro-electromechanical element is defined. Therein the elementcomprises:

a first electrode in the metallisation layer;

a second electrode in a second level metal region, which secondelectrode faces the first electrode and is substantially free-standing,such that it is movable towards the first electrode; and

at least one via extending from the second level metal regions to themetal regions, the via providing an electrical connection and mechanicalsupport, a perpendicular projection of the metal region on themetallisation layer substantially non-overlapping with the firstelectrode.

Micro-electromechanical elements are known per se, for example from WO-A01/61848. They are proposed for instance as switches and tunablecapacitors for applications in the RF domain. With this embodiment, suchelements may be manufactured as discrete elements, be provided inpassive networks, or inside an interconnect structure of an integratedcircuit. Therewith the seed layer can be used as an etch stop layer,that protects the underlying first isolating layer. Preferably the firstisolating layer is not removed, but maintained so as to act asdielectric layer. The element is in that case a tunable capacitor ofwhich the tuning range is enhanced considerably, in comparison with anembodiment without dielectric layer. Alternatively, The first isolatinglayer may be chosen so as to act as a protecting and/or anti-stickinglayer. It could then even contain conductive particles. This is suitableif the element is to be used as a switch.

In the embodiment of the multilevel structure, it is preferred that thesecond and third isolating layers are removed in a single step. It istherefore preferred that these isolating layers contain the samematerial, which is a photoresist by preference. The seed layers areremoved in another removal step. The removal preferably takes place bymeans of etching. If the seed layers contain the same material as themetal regions, such as copper, or if the etchant for the seed layersalso etches the metal regions, it is preferred that the definition ofthe patterns is modified thereto, i.e. the patterns are designed largerso as to allow a size reduction during the removal steps.

The multilevel structure formed may be present on a planarizedsubstrate. Alternatively, the substrate may contain cavities, whereinthe multilevel structure is provided. Such structure can be used toprovide a cap on top of the structure. Also the sidewalls of such astructure may provide additional mechanical strength. Further on,spacers and a capping layer may be present on the substrate to provide acover for the multilevel structure. The capping layer may be provided ontop of the metal regions before the removal of the isolating layers andthe one or more seed layers. In that case it must be etch resistantagainst the etchants used. A suitable combination is for instance aceramic or silicon oxide capping layer, with polymeric photoresists andcopper metal layers.

The invention is described further hereinafter, by way of example only,with reference to the accompanying drawings in which:

FIGS. 1-4 illustrate four steps in a semiconductor metallization processembodying the present invention;

FIGS. 5-8 demonstrates similar steps in accordance with a furtherprocessing stage, according to an embodiment of the present invention;

FIGS. 9-13 illustrate five further steps that can be employed subsequentto the steps of FIGS. 5-8.

FIG. 14 shows a diagrammatical cross-sectional view of a step in asecond embodiment of the method of the invention;

FIG. 15 shows a diagrammatical cross-sectional view of the deviceresulting from the second embodiment; and

FIG. 16 shows a diagrammatical cross-sectional view of a deviceresulting from a third embodiment of the invention.

Before turning to the particular embodiments described in relation tothe drawings, it should be appreciated that the present invention canadvantageously provide for a manner of processing back-end contacts andmetallization layers by way of a single metallization step. For example,first the contact holes are patterned. This can be done in an isolatinglow-k dielectric material or a photo resist layer, or any other materialwith comparable properties, which can be removed in a later stage. Ontop of this patterned layer a metal seed layer is deposited. Then, themetallization layer is patterned on the same way like the contact holes.Hereafter, the seed layer is used to selectively grow the metal untilthe contact holes and the metallization layers are sufficiently filled.This process can be used again to define the following contact-metalinterconnecting layer. After all the contact-metal interconnectionlayers are defined, the top isolating layer, defining themetal-interconnects, can be selectively removed. Next the thin seedlayer is removed selectively and then the underlying isolating layer,defining the contact holes, has to be removed again. This has to berepeated for every contact-metal stage grown, resulting in a completeinterconnect stack with air as the dielectric material.

This process is now described in detail.

Turning first to FIG. 1 there is illustrated an initial step in aprocess embodying the present invention in which a patterned firstisolation layer 10 has been provided on a substrate 12. The firstisolation layer 10 can comprise a photoresist material, a dielectricmaterial or indeed any other appropriate material with comparableproperties and, in the present illustrated example, the first isolationlayer 10 has been patterned so as to include contact holes 14 whichextend down to the substrate 12.

With regard to FIG. 2, there is illustrated a next step in thisembodiment in which a metal seed layer 16 is deposited on top of thefirst isolation layer 10 and in the contact holes 14. This seed layer 16serves as a conductive seed layer for subsequent metal growth which can,for example, be based on metal standard plating techniques.

With regard to FIG. 3, the next step in this embodiment of the presentinvention involves the formation of a second patterned isolating layer18 which is formed on the aforementioned seed layer 16. This secondisolating layer 18 is patterned in the illustrated embodiment so thatonly isolated portions remain located on portions of the first isolationlayer 10 which have remained subsequent to the patterning of the saidfirst isolation layer 10.

The formation of the first and second isolation layers 10, 18 and theseed layer 16 in this manner provides for a particularly advantageousfeature of the present invention in that it will be appreciated that theremaining regions of the second isolation layer 18 serve to coverunderlying regions of the seed layer 16 to prevent subsequent metalgrowth on such covered regions.

The metallization, such as the formation of a metal layer formed bystandard metal plating techniques, is conducted so as to selectivelygrow the metal upon those regions of the seed layer 16 which remainaccessible by the electrolyte material. This is illustrated in FIG. 4and, from the above discussion in relation to FIG. 3, it will beappreciated that the metal therefore grows within the contact holes 14and also serves to form metal lines 20 extending between the contactholes 14.

As will be appreciated, due to the structure formed and as illustratedin FIG. 3, no metal growth occurs on the upper surface of the remainingregions of the second patterned isolating layer 18 and so the growth ofthe metal illustrated in FIG. 4 serves to effectively fill the contactholes 14 and also the regions which will serve to define metal linesproviding for contact between the metal grown in the contact holes 14.As illustrated in FIG. 4, the contact holes and metal line regions areadvantageously filled in a self-aligned manner such that it can bereadily possible to avoid incorporating a separate planarisation step inorder to achieve the metallized structure illustrated in FIG. 4. Thisserves to simplify the semiconductor Metallization process embodying thepresent invention.

The isolating layers can, if required, be removed at this stage suchthat a shallow stack structure comprising the deposited metal 20remains.

However, the steps according to as illustrated in FIGS. 1-4 above can beeffectively repeated so that a further set of first and second isolationlayers—again with a seed layer formed therebetween, are formed on thestructure illustrated on FIG. 4.

This is illustrated with reference to FIG. 5 in which a third isolatinglayer 10′ is formed and patterned so as to provide a further set ofcontact holes 14′ and, subsequently, as illustrated in FIG. 6, a furthermetal seed layer 16′ is formed on top of this third isolating layer 10′and in the contact holes 14′.

As illustrated in FIG. 7, the fourth isolating layer 18′ is formed andpatterned on the seed layer 16′ so as to remain as illustrated in FIG. 7and, as with the step illustrated in FIG. 4, this further structuredefined by this further set of third 10′ and fourth 18′ isolating layersis then subjected to a standard metal plating technique. As illustratedin FIG. 8, such a further single metallization step leads to theformation of metal in the further contact holes 14′ and also providesfor second level metal regions 20′ as before. As will be appreciated,the metal layer is again grown where the seed layer is in contact withthe electrolyte and again, this further metallization structure isformed in an advantageously self-aligned manner not necessarilyrequiring an additional planarisation step to arrive at the structureillustrated in FIG. 8.

The steps illustrated in FIGS. 9-13 relate to the removal of the twosets of first and second isolating layers.

With reference first to FIG. 9, the upmost, i.e. fourth or even furtherisolating layer 18′ can be removed by any standard technique untilexposing the seed layer 16′ which serves to shield the underlyingportion of the third isolating layer 10′. This bare seed layer portionis selectively removed so as to expose the underlying third isolatinglayer 10′. It will of course be appreciated that the removal of the seedlayer also effects the metallization structure since it consists ofeffectively the same material. However, the amount of material that isremoved to sufficiently strip the seed layer, and thus the correspondingamount that is removed from the metallization structure, will not haveany significant influence on the resulting metal structure.

Subsequent to removal of the further seed layer 16′, the said thirdisolation layer 10′ and the underlying second isolating layer 18 of thefirst set of layers are then removed until the initial seed layer 16shielding the underlying initial first isolation layer 10 is thenexposed as illustrated in FIG. 11.

Again, the exposed initial seed layer 16 is selectively removed asillustrated in FIG. 12 so as to expose the initial first isolation layer10 as illustrated in Step 12.

The removal of this initial first isolation layer 10 leads to a finalmetallization stack structure 22 which is illustrated formed on thesubstrate 12 in FIG. 13.

This resulting structure comprises a complete metallization stackconsisting solely of metal and with air being available as the ultimateisolating dielectric.

As will be appreciated, the set of steps illustrated in FIGS. 1-4 andthen again in FIGS. 5-8, as required, can be repeated to form an evenmore elaborate stacked interconnect structure then that illustrated inFIG. 13. In any case, it should be appreciated that for each contacthole layer and metal interconnect layer, only one metallization step isrequired such that, for the structure illustrated in FIG. 13, only twosuch Metallization steps were required to arrive at the metallizationstack illustrated.

That is, first a lithographic step is employed to pattern a contactlevel in the structure then, subsequent to the application of the seedlayer, a second lithographic step can then be employed to pattern theso-called interconnect-metal layer which is then grown in a self-alignedmanner since the seed layer is covered at the areas where it is desiredto prevent metal growth.

FIG. 14 shows a cross-sectional drawing of a stage in another embodimentof the method of the invention. FIG. 15 shows the resulting device 24.In the method a metallisation layer 11 has been defined at the surface 1of the substrate 12. After deposition and patterning of themetallisation layer, the resulting substrate is planarized. However,this is not necessary. Thereafter the first isolation layer 10 has beendeposited, for example with Chemical-Vapour Deposition. The firstisolation layer 10 is patterned so that it is only present where acapacitor 13 is to be defined. Thereafter the seed layer 16 is applied.This seed layer 16 seals the first isolation layer 10 and is present onareas of the metallisation layer 11 that are exposed. The secondisolation layer 18 being a photoresist is provided thereon by means ofspincoating. The metal regions 20 can now be grown, for instance withelectroplating. However, it is preferred as shown in FIG. 14 that anadditional seed layer 26 and an additional second isolation layer 28 areapplied. The additional seed layer 26 is applied without beingpatterned. The additional second isolation layer 28 is patternedaccording to the same pattern as the second isolation layer 18, i.e. noadditional photolithographic mask is required.

After growing the metal regions 20 non-shown third and fourth isolatinglayers 10′, 18′, a non-shown further seed layer 16′ and second levelmetal regions 20′ are provided. This is realized as described withreference to the FIGS. 5-8. Thereafter, the second, third and fourthisolating layers 18, 28, 10′ and 18′ and the seed layers 16, 26, 16′ areremoved by means of etching.

FIG. 15 shows a cross-sectional diagrammatic view of the resultingdevice 24. Therein, a capacitor 13 is present with a first electrode 111in the metallisation layer and a second electrode 201 in a metal region.The first isolating layer 10 is present as dielectricum between theelectrodes 111, 201.

FIG. 16 shows a cross-sectional diagrammatic view of another device 26that is manufactured with the method of the invention. According to thisembodiment, a metallisation layer 11 is provided on the surface 1 of thesubstrate 12. Subsequently the first isolation layer 10, and the seedlayer 16 are provided. After providing the non-shown second isolationlayer metal regions 20 are formed. After growing the metal regions 20not-shown third and fourth isolating layers 10′, 18′, a further seedlayer 16′ and second level metal regions 20′ are provided. This isrealized as described with reference to the FIGS. 5-8. Thereafter, thesecond, third and fourth isolating layers 18, 28, 10′ and 18′ and theseed layers 16, 26, 16′ are removed by means of etching. As a result amicro-electromechanical element is defined with a first electrode 111and a second electrode 201′. This second electrode 201′ faces the firstelectrode 111, i.e. a perpendicular projection of the second electrode201′ on the metallisation layer 11 substantially overlaps with the firstelectrode 111. Further on, it is substantially free-standing, such thatit is movable towards the first electrode 111. This is realized in anadequate patterning of the fourth isolation layer, i.e. in the directionperpendicular to the plane of the drawing the second electrode 201′extends to an extent that the vias 141 do not. These vias 141 extendfrom the second level metal regions 20′ to the regions 20. The metalregions 20 are such defined that a perpendicular projection of the metalregion 20 on the metallisation layer 11 lets the first electrode 111substantially free.

What is claimed is:
 1. A method of manufacturing an electronic deviceprovided with metal regions, that are mutually separated by air spaces,which method comprises the steps of: forming a patterned first isolatinglayer on a substrate surface; depositing a metal seed layer so that itcovers the first isolating layer and exposed areas of the substratesurface; and forming metal regions upon the exposed seed layer;characterised in that a second patterned isolating layer is formed onthe seed layer according to a second pattern, a perpendicular projectionof which on the substrate surface has an overlap with the firstisolating layer; the metal regions are formed such that they fill thepatterns defined by the first and the second isolating layers, and thesecond isolating layer and the seed layer are removed after forming ofthe metal regions, therewith obtaining the air spaces, the seed layerbeing removed in so far as it is not covered by the metal regions.
 2. Amethod according to claim 1, characterized in that after removal of theseed layer the first isolating layer is removed.
 3. A method accordingto claim 1, characterized in that a metallisation layer is appliedbefore forming the first patterned isolating layer.
 4. A methodaccording to claim 3, characterized in that a capacitor is formed with afirst electrode in the metallisation layer, a second electrode in ametal region and the first isolating layer as an intermediatedielectricum having a relative dielectric constant larger than 7.0.
 5. Amethod according to claim 1, characterized in that before removal of thesecond isolating layer it comprises the steps of: forming a thirdpatterned isolating layer on the metal regions; depositing an additionalmetal seed layer so that it covers the third patterned isolating layerand exposed areas of the metal regions; forming a fourth patternedisolating layer on the additional seed layer according to a fourthpattern; forming second level metal regions upon the exposed seed layer,so as to fill the pattern defined by the third and the fourth isolatinglayers; and removing the fourth isolating layer, the additional metalseed layer, in so far as the seed layer is not covered by the formedsecond level metal regions, and the third isolating layer.
 6. A methodaccording to claim 5, characterized in that a micro-electromechanicalelement is defined, the element comprising: a first electrode in themetallisation layer; a second electrode in a second level metal region,which second electrode faces the first electrode and is substantiallyfree-standing, such that it is movable towards the first electrode; andat least one via extending from the second level metal regions to themetal regions, the via providing an electrical connection and mechanicalsupport, a perpendicular projection of the metal region on themetallisation layer substantially non-overlapping with the firstelectrode.
 7. A method according to claim 5, characterized in that thesecond and third isolating layer are removed in a single step.
 8. Amethod according to claim 1, characterized in that the pattern formed inthe first isolation layer includes contact holes or vias extending tothe substrate surface.
 9. A method according to claim 1, characterizedin that the substrate comprises a plurality of semiconductor elements.